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Esta questão foi aplicada no ano de 2017 pela banca FCC no concurso para TRF - 5ª REGIÃO. A questão aborda conhecimentos da disciplina de Hardware e Arquitetura de Computadores, especificamente sobre Memória em Arquitetura de Computadores.
Esta é uma questão de múltipla escolha com 5 alternativas. Teste seus conhecimentos e selecione a resposta correta.
A typical computer system provides a hierarchy of different types of memories for data storage. Consider the statements below.
I. The hard drive has a local data cache. Because the hard drive access speed is so much slower, disk access are normally done asynchronously at the hardware level. The hard drive controller will acknowledge the instruction right away, and will take sometime to populate the disk cache with the requested data block, and then, at a later time, raise an interrupt to notify the interested party that the data access is complete. This model of interrupt based data transfer is asynchronous.
II. The cache is made up of small chunks of mirrored main memory. The size of these chunks is called the line size, and is typically something like 32 or 64 bytes. The cache can load and store memory in sizes a multiple of a cache line. Caches have their own hierarchy, commonly termed L1, L2 and L3. L1 cache is the fastest and smallest; L2 is bigger and slower, and L3 more so.
III. Internal register in a CPU is used for holding variables and temporary results. Internal registers have a very small storage; however they can be accessed instantly. Accessing data from the internal register is the fastest way to access memory. Most registers are implemented as an array of DRAM cells. DRAM is a type of RAM that is much faster and more reliable than the SRAM, which is used for main memory because of its lower cost and smaller space consumption. DRAM does not need to be electrically refreshed as does SRAM.
The correct statement (s)